Systems and devices for accessing a state machine

ABSTRACT

A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. application Ser. No. 15/534,978, entitled “Systems and Devices For Accessing A State Machine,” and filed Jun. 9, 2017, now U.S. Pat. No. 10,430,210 which issued on Oct. 1, 2019, which is a national phase application of U.S. Application No. PCT/US15/67914, entitled “Systems and Devices For Accessing A State Machine,” and filed on Dec. 29, 2015, which claims priority to the provisional application U.S. Application No. 62/098,165 entitled “Systems and Devices For Accessing A State Machine,” and filed on Dec. 30, 2014, the entirety of which is incorporated by reference herein for all purposes.

BACKGROUND Field of Invention

Embodiments of the invention relate generally to electronic devices and, more specifically, in certain embodiments, to electronic devices with parallel devices for data analysis.

Description of Related Art

Complex pattern recognition can be inefficient to perform on a conventional von Neumann based computer. A biological brain, in particular a human brain, however, is adept at performing pattern recognition. Current research suggests that a human brain performs pattern recognition using a series of hierarchically organized neuron layers in the neocortex. Neurons in the lower layers of the hierarchy analyze “raw signals” from, for example, sensory organs, while neurons in higher layers analyze signal outputs from neurons in the lower levels. This hierarchical system in the neocortex, possibly in combination with other areas of the brain, accomplishes the complex pattern recognition that enables humans to perform high level functions such as spatial reasoning, conscious thought, and complex language.

In the field of computing, pattern recognition tasks are increasingly challenging. Ever larger volumes of data are transmitted between computers, and the number of patterns that users wish to identify is increasing. For example, spam or malware are often detected by searching for patterns in a data stream, e.g., particular phrases or pieces of code. The number of patterns increases with the variety of spam and malware, as new patterns may be implemented to search for new variants. Searching a data stream for each of these patterns can form a computing bottleneck. Often, as the data stream is received, it is searched for each pattern, one at a time. The delay before the system is ready to search the next portion of the data stream increases with the number of patterns. Thus, pattern recognition may slow the receipt of data.

Hardware has been designed to search a data stream for patterns, but this hardware often is unable to process adequate amounts of data in an amount of time given. Some devices configured to search a data stream do so by distributing the data stream among a plurality of circuits. The circuits each determine whether the data stream matches a portion of a pattern. Often, a large number of circuits operate in parallel, each searching the data stream at generally the same time. The system may then further process the results from these circuits, to arrive at the final results. These “intermediate results”, however, can be larger than the original input data, which may pose issues for the system. The ability to use a cascaded circuits approach, similar to the human brain, offers one potential solution to this problem. However, there has not been a system that effectively allows for performing pattern recognition in a manner more comparable to that of a biological brain. Development of such a system is desirable.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates an example of system having a state machine engine, according to various embodiments.

FIG. 2 illustrates an example of an FSM lattice of the state machine engine of FIG. 1, according to various embodiments.

FIG. 3 illustrates an example of a block of the FSM lattice of FIG. 2, according to various embodiments.

FIG. 4 illustrates an example of a row of the block of FIG. 3, according to various embodiments.

FIG. 4A illustrates a block as in FIG. 3 having counters in rows of the block, according to various embodiments.

FIG. 5 illustrates an example of a Group of Two of the row of FIG. 4, according to embodiments.

FIG. 6 illustrates an example of a finite state machine graph, according to various embodiments.

FIG. 7 illustrates an example of two-level hierarchy implemented with FSM lattices, according to various embodiments.

FIG. 7A illustrates a second example of two-level hierarchy implemented with FSM lattices, according to various embodiments.

FIG. 8 illustrates an example of a method for a compiler to convert source code into a binary file for programming of the FSM lattice of FIG. 2, according to various embodiments.

FIG. 9 illustrates a state machine engine, according to various embodiments.

FIG. 10 illustrates an illustrates a second example of a system having a state machine engine, according to various embodiments.

DETAILED DESCRIPTION

Turning now to the figures, FIG. 1 illustrates an embodiment of a processor-based system, generally designated by reference numeral 10. The system 10 may be any of a variety of types such as a desktop computer, laptop computer, pager, cellular phone, personal organizer, portable audio player, control circuit, camera, etc. The system 10 may also be a network node, such as a router, a server, or a client (e.g., one of the previously-described types of computers). The system 10 may be some other sort of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (The terms used to describe these various examples of systems, like many of the other terms used herein, may share some referents and, as such, should not be construed narrowly in virtue of the other items listed.)

In a typical processor-based device, such as the system 10, a processor 12, such as a microprocessor, controls the processing of system functions and requests in the system 10. Further, the processor 12 may comprise a plurality of processors that share system control. The processor 12 may be coupled directly or indirectly to each of the elements in the system 10, such that the processor 12 controls the system 10 by executing instructions that may be stored within the system 10 or external to the system 10.

In accordance with the embodiments described herein, the system 10 includes a state machine engine 14, which may operate under control of the processor 12. The state machine engine 14 may employ any one of a number of state machine architectures, including, but not limited to Mealy architectures, Moore architectures, Finite State Machines (FSMs), Deterministic FSMs (DFSMs), Bit-Parallel State Machines (BPSMs), etc. Though a variety of architectures may be used, for discussion purposes, the application refers to FSMs. However, those skilled in the art will appreciate that the described techniques may be employed using any one of a variety of state machine architectures.

As discussed further below, the state machine engine 14 may include a number of (e.g., one or more) finite state machine (FSM) lattices (e.g., core of a chip). For purposes of this application the term “lattice” refers to an organized framework (e.g., routing matrix, routing network, frame) of elements (e.g., Boolean cells, counter cells, state machine elements, state transition elements). Furthermore, the “lattice” may have any suitable shape, structure, or hierarchical organization (e.g., grid, cube, spherical, cascading). Each FSM lattice may implement multiple FSMs that each receive and analyze the same data in parallel. Further, the FSM lattices may be arranged in groups (e.g., clusters), such that clusters of FSM lattices may analyze the same input data in parallel. Further, clusters of FSM lattices of the state machine engine 14 may be arranged in a hierarchical structure wherein outputs from state machine lattices on a lower level of the hierarchical structure may be used as inputs to state machine lattices on a higher level. By cascading clusters of parallel FSM lattices of the state machine engine 14 in series through the hierarchical structure, increasingly complex patterns may be analyzed (e.g., evaluated, searched, etc.).

Further, based on the hierarchical parallel configuration of the state machine engine 14, the state machine engine 14 can be employed for complex data analysis (e.g., pattern recognition or other processing) in systems that utilize high processing speeds. For instance, embodiments described herein may be incorporated in systems with processing speeds of 1 GByte/sec. Accordingly, utilizing the state machine engine 14, data from high speed memory devices or other external devices may be rapidly analyzed. The state machine engine 14 may analyze a data stream according to several criteria (e.g., search terms), at about the same time, e.g., during a single device cycle. Each of the FSM lattices within a cluster of FSMs on a level of the state machine engine 14 may each receive the same search term from the data stream at about the same time, and each of the parallel FSM lattices may determine whether the term advances the state machine engine 14 to the next state in the processing criterion. The state machine engine 14 may analyze terms according to a relatively large number of criteria, e.g., more than 100, more than 110, or more than 10,000. Because they operate in parallel, they may apply the criteria to a data stream having a relatively high bandwidth, e.g., a data stream of greater than or generally equal to 1 GByte/sec, without slowing the data stream.

In one embodiment, the state machine engine 14 may be configured to recognize (e.g., detect) a great number of patterns in a data stream. For instance, the state machine engine 14 may be utilized to detect a pattern in one or more of a variety of types of data streams that a user or other entity might wish to analyze. For example, the state machine engine 14 may be configured to analyze a stream of data received over a network, such as packets received over the Internet or voice or data received over a cellular network. In one example, the state machine engine 14 may be configured to analyze a data stream for spam or malware. The data stream may be received as a serial data stream, in which the data is received in an order that has meaning, such as in a temporally, lexically, or semantically significant order. Alternatively, the data stream may be received in parallel or out of order and, then, converted into a serial data stream, e.g., by reordering packets received over the Internet. In some embodiments, the data stream may present terms serially, but the bits expressing each of the terms may be received in parallel. The data stream may be received from a source external to the system 10, or may be formed by interrogating a memory device, such as the memory 16, and forming the data stream from data stored in the memory 16. In other examples, the state machine engine 14 may be configured to recognize a sequence of characters that spell a certain word, a sequence of genetic base pairs that specify a gene, a sequence of bits in a picture or video file that form a portion of an image, a sequence of bits in an executable file that form a part of a program, or a sequence of bits in an audio file that form a part of a song or a spoken phrase. The stream of data to be analyzed may include multiple bits of data in a binary format or other formats, e.g., base ten, ASCII, etc. The stream may encode the data with a single digit or multiple digits, e.g., several binary digits.

As will be appreciated, the system 10 may include memory 16. The memory 16 may include volatile memory, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous DRAM (SDRAM), Double Data Rate DRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM etc. The memory 16 may also include non-volatile memory, such as read-only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, polysilicon floating gate based memory, and/or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.) to be used in conjunction with the volatile memory. The memory 16 may include one or more memory devices, such as DRAM devices, that may provide data to be analyzed by the state machine engine 14. As used herein, the term “provide” may generically refer to direct, input, insert, issue, route, send, transfer, transmit, generate, give, make available, move, output, pass, place, read out, write, etc. Such devices may be referred to as or include solid state drives (SSD's), MultimediaMediaCards (MMC's), SecureDigital (SD) cards, CompactFlash (CF) cards, or any other suitable device. Further, it should be appreciated that such devices may couple to the system 10 via any suitable interface, such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Small Computer System Interface (SCSI), IEEE 1394 (Firewire), or any other suitable interface. To facilitate operation of the memory 16, such as the flash memory devices, the system 10 may include a memory controller (not illustrated). As will be appreciated, the memory controller may be an independent device or it may be integral with the processor 12. Additionally, the system 10 may include an external storage 18, such as a magnetic storage device. The external storage may also provide input data to the state machine engine 14.

The system 10 may include a number of additional elements. For instance, a compiler 20 may be used to configure (e.g., program) the state machine engine 14, as described in more detail with regard to FIG. 8. An input device 22 may also be coupled to the processor 12 to allow a user to input data into the system 10. For instance, an input device 22 may be used to input data into the memory 16 for later analysis by the state machine engine 14. The input device 22 may include buttons, switching elements, a keyboard, a light pen, a stylus, a mouse, and/or a voice recognition system, for instance. An output device 24, such as a display may also be coupled to the processor 12. The display 24 may include an LCD, a CRT, LEDs, and/or an audio display, for example. They system may also include a network interface device 26, such as a Network Interface Card (NIC), for interfacing with a network, such as the Internet. As will be appreciated, the system 10 may include many other components, depending on the application of the system 10.

FIGS. 2-5 illustrate an example of a FSM lattice 30. In an example, the FSM lattice 30 comprises an array of blocks 32. As will be described, each block 32 may include a plurality of selectively couple-able hardware elements (e.g., configurable elements and/or special purpose elements) that correspond to a plurality of states in a FSM. Similar to a state in a FSM, a hardware element can analyze an input stream and activate a downstream hardware element, based on the input stream.

The configurable elements can be configured (e.g., programmed) to implement many different functions. For instance, the configurable elements may include state transition elements (STEs) 34, 36 (shown in FIG. 5) that function as data analysis elements and are hierarchically organized into rows 38 (shown in FIGS. 3 and 4) and blocks 32 (shown in FIGS. 2 and 3). The STEs each may be considered an automaton, e.g., a machine or control mechanism designed to follow automatically a predetermined sequence of operations or respond to encoded instructions. Taken together, the STEs form an automata processor as state machine engine 14. To route signals between the hierarchically organized STEs 34, 36, a hierarchy of configurable switching elements can be used, including inter-block switching elements 40 (shown in FIGS. 2 and 3), intra-block switching elements 42 (shown in FIGS. 3 and 4) and intra-row switching elements 44 (shown in FIG. 4).

As described below, the switching elements may include routing structures and buffers. A STE 34, 36 can correspond to a state of a FSM implemented by the FSM lattice 30. The STEs 34, 36 can be coupled together by using the configurable switching elements as described below. Accordingly, a FSM can be implemented on the FSM lattice 30 by configuring the STEs 34, 36 to correspond to the functions of states and by selectively coupling together the STEs 34, 36 to correspond to the transitions between states in the FSM.

FIG. 2 illustrates an overall view of an example of a FSM lattice 30. The FSM lattice 30 includes a plurality of blocks 32 that can be selectively coupled together with configurable inter-block switching elements 40. The inter-block switching elements 40 may include conductors 46 (e.g., wires, traces, etc.) and buffers 48, 50. In an example, buffers 48 and 50 are included to control the connection and timing of signals to/from the inter-block switching elements 40. As described further below, the buffers 48 may be provided to buffer data being sent between blocks 32, while the buffers 50 may be provided to buffer data being sent between inter-block switching elements 40. Additionally, the blocks 32 can be selectively coupled to an input block 52 (e.g., a data input port) for receiving signals (e.g., data) and providing the data to the blocks 32. The blocks 32 can also be selectively coupled to an output block 54 (e.g., an output port) for providing signals from the blocks 32 to an external device (e.g., another FSM lattice 30). The FSM lattice 30 can also include a programming interface 56 to configure (e.g., via an image, program) the FSM lattice 30. The image can configure (e.g., set) the state of the STEs 34, 36. For example, the image can configure the STEs 34, 36 to react in a certain way to a given input at the input block 52. For example, a STE 34, 36 can be set to output a high signal when the character ‘a’ is received at the input block 52.

In an example, the input block 52, the output block 54, and/or the programming interface 56 can be implemented as registers such that writing to or reading from the registers provides data to or from the respective elements. Accordingly, bits from the image stored in the registers corresponding to the programming interface 56 can be loaded on the STEs 34, 36. Although FIG. 2 illustrates a certain number of conductors (e.g., wire, trace) between a block 32, input block 52, output block 54, and an inter-block switching element 40, it should be understood that in other examples, fewer or more conductors may be used.

FIG. 3 illustrates an example of a block 32. A block 32 can include a plurality of rows 38 that can be selectively coupled together with configurable intra-block switching elements 42. Additionally, a row 38 can be selectively coupled to another row 38 within another block 32 with the inter-block switching elements 40. A row 38 includes a plurality of STEs 34, 36 organized into pairs of configurable elements that are referred to herein as groups of two (GOTs) 60. In an example, a block 32 comprises sixteen (16) rows 38.

FIG. 4 illustrates an example of a row 38. A GOT 60 can be selectively coupled to other GOTs 60 and any other elements (e.g., a special purpose element 58) within the row 38 by configurable intra-row switching elements 44. A GOT 60 can also be coupled to other GOTs 60 in other rows 38 with the intra-block switching element 42, or other GOTs 60 in other blocks 32 with an inter-block switching element 40. In an example, a GOT 60 has a first and second input 62, 64, and an output 66. The first input 62 is coupled to a first STE 34 of the GOT 60 and the second input 64 is coupled to a second STE 36 of the GOT 60, as will be further illustrated with reference to FIG. 5.

In an example, the row 38 includes a first and second plurality of row interconnection conductors 68, 70. In an example, an input 62, 64 of a GOT 60 can be coupled to one or more row interconnection conductors 68, 70, and an output 66 can be coupled to one or more row interconnection conductor 68, 70. In an example, a first plurality of the row interconnection conductors 68 can be coupled to each STE 34, 36 of each GOT 60 within the row 38. A second plurality of the row interconnection conductors 70 can be coupled to only one STE 34, 36 of each GOT 60 within the row 38, but cannot be coupled to the other STE 34, 36 of the GOT 60. In an example, a first half of the second plurality of row interconnection conductors 70 can couple to first half of the STEs 34, 36 within a row 38 (one STE 34 from each GOT 60) and a second half of the second plurality of row interconnection conductors 70 can couple to a second half of the STEs 34, 36 within a row 38 (the other STE 34, 36 from each GOT 60), as will be better illustrated with respect to FIG. 5. The limited connectivity between the second plurality of row interconnection conductors 70 and the STEs 34, 36 is referred to herein as “parity”. In an example, the row 38 can also include a special purpose element 58 such as a counter, a configurable Boolean logic element, look-up table, RAM, a field configurable gate array (FPGA), an application specific integrated circuit (ASIC), a configurable processor (e.g., a microprocessor), or other element for performing a special purpose function.

In an example, the special purpose element 58 comprises a counter (also referred to herein as counter 58). In an example, the counter 58 comprises a 12-bit configurable down counter. The 12-bit configurable counter 58 has a counting input, a reset input, and zero-count output. The counting input, when asserted, decrements the value of the counter 58 by one. The reset input, when asserted, causes the counter 58 to load an initial value from an associated register. For the 12-bit counter 58, up to a 12-bit number can be loaded in as the initial value. When the value of the counter 58 is decremented to zero (0), the zero-count output is asserted. The counter 58 also has at least two modes, pulse and hold. When the counter 58 is set to pulse mode, the zero-count output is asserted when the counter 58 reaches zero. For example, the zero-count output is asserted during the processing of an immediately subsequent next data byte, which results in the counter 58 being offset in time with respect to the input character cycle. After the next character cycle, the zero-count output is no longer asserted. In this manner, for example, in the pulse mode, the zero-count output is asserted for one input character processing cycle. When the counter 58 is set to hold mode the zero-count output is asserted during the clock cycle when the counter 58 decrements to zero, and stays asserted until the counter 58 is reset by the reset input being asserted.

In another example, the special purpose element 58 comprises Boolean logic. For example, the Boolean logic may be used to perform logical functions, such as AND, OR, NAND, NOR, Sum of Products (SoP), Negated-Output Sum of Products (NSoP), Negated-Output Product of Sume (NPoS), and Product of Sums (PoS) functions. This Boolean logic can be used to extract data from terminal state STEs (corresponding to terminal nodes of a FSM, as discussed later herein) in FSM lattice 30. The data extracted can be used to provide state data to other FSM lattices 30 and/or to provide configuring data used to reconfigure FSM lattice 30, or to reconfigure another FSM lattice 30.

FIG. 4A is an illustration of an example of a block 32 having rows 38 which each include the special purpose element 58. For example, the special purpose elements 58 in the block 32 may include counter cells 58A and Boolean logic cells 58B. While only the rows 38 in row positions 0 through 4 are illustrated in FIG. 4A (e.g., labeled 38A through 38E), each block 32 may have any number of rows 38 (e.g., 16 rows 38), and one or more special purpose elements 58 may be configured in each of the rows 38. For example, in one embodiment, counter cells 58A may be configured in certain rows 38 (e.g., in row positions 0, 4, 8, and 12), while the Boolean logic cells 58B may be configured in the remaining of the 16 rows 38 (e.g., in row positions 1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15, and 16). The GOT 60 and the special purpose elements 58 may be selectively coupled (e.g., selectively connected) in each row 38 through intra-row switching elements 44, where each row 38 of the block 32 may be selectively coupled with any of the other rows 38 of the block 32 through intra-block switching elements 42.

In some embodiments, each active GOT 60 in each row 38 may output a signal indicating whether one or more conditions are detected (e.g., a search result is detected), and the special purpose element 58 in the row 38 may receive the GOT 60 output to determine whether certain quantifiers of the one or more conditions are met and/or count a number of times a condition is detected. For example, quantifiers of a count operation may include determining whether a condition was detected at least a certain number of times, determining whether a condition was detected no more than a certain number of times, determining whether a condition was detected exactly a certain number of times, and determining whether a condition was detected within a certain range of times.

Outputs from the counter 58A and/or the Boolean logic cell 58B may be communicated through the intra-row switching elements 44 and the intra-block switching elements 42 to perform counting or logic with greater complexity. For example, counters 58A may be configured to implement the quantifiers, such as asserting an output only when a condition is detected an exact number of times. Counters 58A in a block 32 may also be used concurrently, thereby increasing the total bit count of the combined counters to count higher numbers of a detected condition. Furthermore, in some embodiments, different special purpose elements 58 such as counters 58A and Boolean logic cells 58B may be used together. For example, an output of one or more Boolean logic cells 58B may be counted by one or more counters 58A in a block 32.

FIG. 5 illustrates an example of a GOT 60. The GOT 60 includes a first STE 34 and a second STE 36 coupled to intra-group circuitry 37. For example, the first STE 34 and a second STE 36 may have inputs 62, 64 and outputs 72, 74 coupled to an OR gate 76 and a 3-to-1 multiplexer 78 of the intra-group circuitry 37. The 3-to-1 multiplexer 78 can be set to couple the output 66 of the GOT 60 to either the first STE 34, the second STE 36, or the OR gate 76. The OR gate 76 can be used to couple together both outputs 72, 74 to form the common output 66 of the GOT 60. In an example, the first and second STE 34, 36 exhibit parity, as discussed above, where the input 62 of the first STE 34 can be coupled to some of the row interconnection conductors 68 and the input 64 of the second STE 36 can be coupled to other row interconnection conductors 70 the common output 66 may be produced which may overcome parity problems. In an example, the two STEs 34, 36 within a GOT 60 can be cascaded and/or looped back to themselves by setting either or both of switching elements 79. The STEs 34, 36 can be cascaded by coupling the output 72, 74 of the STEs 34, 36 to the input 62, 64 of the other STE 34, 36. The STEs 34, 36 can be looped back to themselves by coupling the output 72, 74 to their own input 62, 64. Accordingly, the output 72 of the first STE 34 can be coupled to neither, one, or both of the input 62 of the first STE 34 and the input 64 of the second STE 36. Additionally, as each of the inputs 62, 64 may be coupled to a plurality of row routing lines, an OR gate may be utilized to select any of the inputs from these row routing lines along inputs 62, 64, as well as the outputs 72, 74.

In an example, each state transition element 34, 36 comprises a plurality of memory cells 80, such as those often used in dynamic random access memory (DRAM), coupled in parallel to a detect line 82. One such memory cell 80 comprises a memory cell that can be set to a data state, such as one that corresponds to either a high or a low value (e.g., a 1 or 0). The output of the memory cell 80 is coupled to the detect line 82 and the input to the memory cell 80 receives signals based on data on the data stream line 84. In an example, an input at the input block 52 is decoded to select one or more of the memory cells 80. The selected memory cell 80 provides its stored data state as an output onto the detect line 82. For example, the data received at the input block 52 can be provided to a decoder (not shown) and the decoder can select one or more of the data stream lines 84. In an example, the decoder can convert an 8-bit ACSII character to the corresponding 1 of 256 data stream lines 84.

A memory cell 80, therefore, outputs a high signal to the detect line 82 when the memory cell 80 is set to a high value and the data on the data stream line 84 selects the memory cell 80. When the data on the data stream line 84 selects the memory cell 80 and the memory cell 80 is set to a low value, the memory cell 80 outputs a low signal to the detect line 82. The outputs from the memory cells 80 on the detect line 82 are sensed by a detection cell 86.

In an example, the signal on an input line 62, 64 sets the respective detection cell 86 to either an active or inactive state. When set to the inactive state, the detection cell 86 outputs a low signal on the respective output 72, 74 regardless of the signal on the respective detect line 82. When set to an active state, the detection cell 86 outputs a high signal on the respective output line 72, 74 when a high signal is detected from one of the memory cells 82 of the respective STE 34, 36. When in the active state, the detection cell 86 outputs a low signal on the respective output line 72, 74 when the signals from all of the memory cells 82 of the respective STE 34, 36 are low.

In an example, an STE 34, 36 includes 256 memory cells 80 and each memory cell 80 is coupled to a different data stream line 84. Thus, an STE 34, 36 can be programmed to output a high signal when a selected one or more of the data stream lines 84 have a high signal thereon. For example, the STE 34 can have a first memory cell 80 (e.g., bit 0) set high and all other memory cells 80 (e.g., bits 1-255) set low. When the respective detection cell 86 is in the active state, the STE 34 outputs a high signal on the output 72 when the data stream line 84 corresponding to bit 0 has a high signal thereon. In other examples, the STE 34 can be set to output a high signal when one of multiple data stream lines 84 have a high signal thereon by setting the appropriate memory cells 80 to a high value.

In an example, a memory cell 80 can be set to a high or low value by reading bits from an associated register. Accordingly, the STEs 34 can be configured by storing an image created by the compiler 20 into the registers and loading the bits in the registers into associated memory cells 80. In an example, the image created by the compiler 20 includes a binary image of high and low (e.g., 1 and 0) bits. The image can configure the FSM lattice 30 to implement a FSM by cascading the STEs 34, 36. For example, a first STE 34 can be set to an active state by setting the detection cell 86 to the active state. The first STE 34 can be set to output a high signal when the data stream line 84 corresponding to bit 0 has a high signal thereon. The second STE 36 can be initially set to an inactive state, but can be set to, when active, output a high signal when the data stream line 84 corresponding to bit 1 has a high signal thereon. The first STE 34 and the second STE 36 can be cascaded by setting the output 72 of the first STE 34 to couple to the input 64 of the second STE 36. Thus, when a high signal is sensed on the data stream line 84 corresponding to bit 0, the first STE 34 outputs a high signal on the output 72 and sets the detection cell 86 of the second STE 36 to an active state. When a high signal is sensed on the data stream line 84 corresponding to bit 1, the second STE 36 outputs a high signal on the output 74 to activate another STE 36 or for output from the FSM lattice 30.

In an example, a single FSM lattice 30 is implemented on a single physical device, however, in other examples two or more FSM lattices 30 can be implemented on a single physical device (e.g., physical chip). In an example, each FSM lattice 30 can include a distinct data input block 52, a distinct output block 54, a distinct programming interface 56, and a distinct set of configurable elements. Moreover, each set of configurable elements can react (e.g., output a high or low signal) to data at their corresponding data input block 52. For example, a first set of configurable elements corresponding to a first FSM lattice 30 can react to the data at a first data input block 52 corresponding to the first FSM lattice 30. A second set of configurable elements corresponding to a second FSM lattice 30 can react to a second data input block 52 corresponding to the second FSM lattice 30. Accordingly, each FSM lattice 30 includes a set of configurable elements, wherein different sets of configurable elements can react to different input data. Similarly, each FSM lattice 30, and each corresponding set of configurable elements can provide a distinct output. In some examples, an output block 54 from a first FSM lattice 30 can be coupled to an input block 52 of a second FSM lattice 30, such that input data for the second FSM lattice 30 can include the output data from the first FSM lattice 30 in a hierarchical arrangement of a series of FSM lattices 30.

In an example, an image for loading onto the FSM lattice 30 comprises a plurality of bits of data for configuring the configurable elements, the configurable switching elements, and the special purpose elements within the FSM lattice 30. In an example, the image can be loaded onto the FSM lattice 30 to configure the FSM lattice 30 to provide a desired output based on certain inputs. The output block 54 can provide outputs from the FSM lattice 30 based on the reaction of the configurable elements to data at the data input block 52. An output from the output block 54 can include a single bit indicating a search result of a given pattern, a word comprising a plurality of bits indicating search results and non-search results to a plurality of patterns, and a state vector corresponding to the state of all or certain configurable elements at a given moment. As described, a number of FSM lattices 30 may be included in a state machine engine, such as state machine engine 14, to perform data analysis, such as pattern-recognition (e.g., speech recognition, image recognition, etc.) signal processing, imaging, computer vision, cryptography, and others.

FIG. 6 illustrates an example model of a finite state machine (FSM) that can be implemented by the FSM lattice 30. The FSM lattice 30 can be configured (e.g., programmed) as a physical implementation of a FSM. A FSM can be represented as a diagram 90, (e.g., directed graph, undirected graph, pseudograph), which contains one or more root nodes 92. In addition to the root nodes 92, the FSM can be made up of several standard nodes 94 and terminal nodes 96 that are connected to the root nodes 92 and other standard nodes 94 through one or more edges 98. A node 92, 94, 96 corresponds to a state in the FSM. The edges 98 correspond to the transitions between the states.

Each of the nodes 92, 94, 96 can be in either an active or an inactive state. When in the inactive state, a node 92, 94, 96 does not react (e.g., respond) to input data. When in an active state, a node 92, 94, 96 can react to input data. An upstream node 92, 94 can react to the input data by activating a node 94, 96 that is downstream from the node when the input data matches criteria specified by an edge 98 between the upstream node 92, 94 and the downstream node 94, 96. For example, a first node 94 that specifies the character ‘b’ will activate a second node 94 connected to the first node 94 by an edge 98 when the first node 94 is active and the character ‘b’ is received as input data. As used herein, “upstream” refers to a relationship between one or more nodes, where a first node that is upstream of one or more other nodes (or upstream of itself in the case of a loop or feedback configuration) refers to the situation in which the first node can activate the one or more other nodes (or can activate itself in the case of a loop). Similarly, “downstream” refers to a relationship where a first node that is downstream of one or more other nodes (or downstream of itself in the case of a loop) can be activated by the one or more other nodes (or can be activated by itself in the case of a loop). Accordingly, the terms “upstream” and “downstream” are used herein to refer to relationships between one or more nodes, but these terms do not preclude the use of loops or other non-linear paths among the nodes.

In the diagram 90, the root node 92 can be initially activated and can activate downstream nodes 94 when the input data matches an edge 98 from the root node 92. Nodes 94 can activate nodes 96 when the input data matches an edge 98 from the node 94. Nodes 94, 96 throughout the diagram 90 can be activated in this manner as the input data is received. A terminal node 96 corresponds to a search result of a sequence of interest in the input data. Accordingly, activation of a terminal node 96 indicates that a sequence of interest has been received as the input data. In the context of the FSM lattice 30 implementing a pattern recognition function, arriving at a terminal node 96 can indicate that a specific pattern of interest has been detected in the input data.

In an example, each root node 92, standard node 94, and terminal node 96 can correspond to a configurable element in the FSM lattice 30. Each edge 98 can correspond to connections between the configurable elements. Thus, a standard node 94 that transitions to (e.g., has an edge 98 connecting to) another standard node 94 or a terminal node 96 corresponds to a configurable element that transitions to (e.g., provides an output to) another configurable element. In some examples, the root node 92 does not have a corresponding configurable element.

As will be appreciated, although the node 92 is described as a root node and nodes 96 are described as terminal nodes, there may not necessarily be a particular “start” or root node and there may not necessarily be a particular “end” or output node. In other words, any node may be a starting point and any node may provide output.

When the FSM lattice 30 is programmed, each of the configurable elements can also be in either an active or inactive state. A given configurable element, when inactive, does not react to the input data at a corresponding data input block 52. An active configurable element can react to the input data at the data input block 52, and can activate a downstream configurable element when the input data matches the setting of the configurable element. When a configurable element corresponds to a terminal node 96, the configurable element can be coupled to the output block 54 to provide an indication of a search result to an external device.

An image loaded onto the FSM lattice 30 via the programming interface 56 can configure the configurable elements and special purpose elements, as well as the connections between the configurable elements and special purpose elements, such that a desired FSM is implemented through the sequential activation of nodes based on reactions to the data at the data input block 52. In an example, a configurable element remains active for a single data cycle (e.g., a single character, a set of characters, a single clock cycle) and then becomes inactive unless re-activated by an upstream configurable element.

A terminal node 96 can be considered to store a compressed history of past search results. For example, the one or more patterns of input data required to reach a terminal node 96 can be represented by the activation of that terminal node 96. In an example, the output provided by a terminal node 96 is binary, for example, the output indicates whether a search result for a pattern of interest has been generated or not. The ratio of terminal nodes 96 to standard nodes 94 in a diagram 90 may be quite small. In other words, although there may be a high complexity in the FSM, the output of the FSM may be small by comparison.

In an example, the output of the FSM lattice 30 can comprise a state vector. The state vector comprises the state (e.g., activated or not activated) of configurable elements of the FSM lattice 30. In another example, the state vector can include the state of all or a subset of the configurable elements whether or not the configurable elements corresponds to a terminal node 96. In an example, the state vector includes the states for the configurable elements corresponding to terminal nodes 96. Thus, the output can include a collection of the indications provided by all terminal nodes 96 of a diagram 90. The state vector can be represented as a word, where the binary indication provided by each terminal node 96 comprises one bit of the word. This encoding of the terminal nodes 96 can provide an effective indication of the detection state (e.g., whether and what sequences of interest have been detected) for the FSM lattice 30.

As mentioned above, the FSM lattice 30 can be programmed to implement a pattern recognition function. For example, the FSM lattice 30 can be configured to recognize one or more data sequences (e.g., signatures, patterns) in the input data. When a data sequence of interest is recognized by the FSM lattice 30, an indication of that recognition can be provided at the output block 54. In an example, the pattern recognition can recognize a string of symbols (e.g., ASCII characters) to, for example, identify malware or other data in network data.

FIG. 7 illustrates an example of hierarchical structure 100, wherein two levels of FSM lattices 30 are coupled in series and used to analyze data. Specifically, in the illustrated embodiment, the hierarchical structure 100 includes a first FSM lattice 30A and a second FSM lattice 30B arranged in series. Each FSM lattice 30 includes a respective data input block 52 to receive data input, a programming interface block 56 to receive configuring signals and an output block 54.

The first FSM lattice 30A is configured to receive input data, for example, raw data at a data input block. The first FSM lattice 30A reacts to the input data as described above and provides an output at an output block. The output from the first FSM lattice 30A is sent to a data input block of the second FSM lattice 30B. The second FSM lattice 30B can then react based on the output provided by the first FSM lattice 30A and provide a corresponding output signal 102 of the hierarchical structure 100. This hierarchical coupling of two FSM lattices 30A and 30B in series provides a means to provide data regarding past search results in a compressed word from a first FSM lattice 30A to a second FSM lattice 30B. The data provided can effectively be a summary of complex matches (e.g., sequences of interest) that were recorded by the first FSM lattice 30A.

FIG. 7A illustrates a second two-level hierarchy 100 of FSM lattices 30A, 30B, 30C, and 30D, which allows the overall FSM 100 (inclusive of all or some of FSM lattices 30A, 30B, 30C, and 30D) to perform two independent levels of analysis of the input data. The first level (e.g., FSM lattice 30A, FSM lattice 30B, and/or FSM lattice 30C) analyzes the same data stream, which includes data inputs to the overall FSM 100. The outputs of the first level (e.g., FSM lattice 30A, FSM lattice 30B, and/or FSM lattice 30C) become the inputs to the second level, (e.g., FSM lattice 30D). FSM lattice 30D performs further analysis of the combination the analysis already performed by the first level (e.g., FSM lattice 30A, FSM lattice 30B, and/or FSM lattice 30C). By connecting multiple FSM lattices 30A, 30B, and 30C together, increased knowledge about the data stream input may be obtained by FSM lattice 30D.

The first level of the hierarchy (implemented by one or more of FSM lattice 30A, FSM lattice 30B, and FSM lattice 30C) can, for example, perform processing directly on a raw data stream. For example, a raw data stream can be received at an input block 52 of the first level FSM lattices 30A, 30B, and/or 30C and the configurable elements of the first level FSM lattices 30A, 30B, and/or 30C can react to the raw data stream. The second level (implemented by the FSM lattice 30D) of the hierarchy can process the output from the first level. For example, the second level FSM lattice 30D receives the output from an output block 54 of the first level FSM lattices 30A, 30B, and/or 30C at an input block 52 of the second level FSM lattice 30D and the configurable elements of the second level FSM lattice 30D can react to the output of the first level FSM lattices 30A, 30B, and/or 30C. Accordingly, in this example, the second level FSM lattice 30D does not receive the raw data stream as an input, but rather receives the indications of search results for patterns of interest that are generated from the raw data stream as determined by one or more of the first level FSM lattices 30A, 30B, and/or 30C. Thus, the second level FSM lattice 30D can implement a FSM 100 that recognizes patterns in the output data stream from the one or more of the first level FSM lattices 30A, 30B, and/or 30C. However, it should also be appreciated that the second level FSM lattice 30D can additionally receive the raw data stream as an input, for example, in conjunction with the indications of search results for patterns of interest that are generated from the raw data stream as determined by one or more of the first level FSM lattices 30A, 30B, and/or 30C. It should be appreciated that the second level FSM lattice 30D may receive inputs from multiple other FSM lattices in addition to receiving output from the one or more of the first level FSM lattices 30A, 30B, and/or 30C. Likewise, the second level FSM lattice 30D may receive inputs from other devices. The second level FSM lattice 30D may combine these multiple inputs to produce outputs. Finally, while only two levels of FSM lattices 30A, 30B, 30C, and 30D are illustrated, it is envisioned that additional levels of FSM lattices may be stacked such that there are, for example, three, four, 10, 100, or more levels of FSM lattices.

FIG. 8 illustrates an example of a method 110 for a compiler to convert source code into an image used to configure a FSM lattice, such as lattice 30, to implement a FSM. Method 110 includes parsing the source code into a syntax tree (block 112), converting the syntax tree into an automaton (block 114), optimizing the automaton (block 116), converting the automaton into a netlist (block 118), placing the netlist on hardware (block 120), routing the netlist (block 122), and publishing the resulting image (block 124).

In an example, the compiler 20 includes an application programming interface (API) that allows software developers to create images for implementing FSMs on the FSM lattice 30. The compiler 20 provides methods to convert an input set of regular expressions in the source code into an image that is configured to configure the FSM lattice 30. The compiler 20 can be implemented by instructions for a computer having a von Neumann architecture. These instructions can cause a processor 12 on the computer to implement the functions of the compiler 20. For example, the instructions, when executed by the processor 12, can cause the processor 12 to perform actions as described in blocks 112, 114, 116, 118, 120, 122, and 124 on source code that is accessible to the processor 12.

In an example, the source code describes search strings for identifying patterns of symbols within a group of symbols. To describe the search strings, the source code can include a plurality of regular expressions (regexes). A regex can be a string for describing a symbol search pattern. Regexes are widely used in various computer domains, such as programming languages, text editors, network security, and others. In an example, the regular expressions supported by the compiler include criteria for the analysis of unstructured data. Unstructured data can include data that is free form and has no indexing applied to words within the data. Words can include any combination of bytes, printable and non-printable, within the data. In an example, the compiler can support multiple different source code languages for implementing regexs including Perl, (e.g., Perl compatible regular expressions (PCRE)), PHP, Java, and .NET languages.

At block 112 the compiler 20 can parse the source code to form an arrangement of relationally connected operators, where different types of operators correspond to different functions implemented by the source code (e.g., different functions implemented by regexes in the source code). Parsing source code can create a generic representation of the source code. In an example, the generic representation comprises an encoded representation of the regexs in the source code in the form of a tree graph known as a syntax tree. The examples described herein refer to the arrangement as a syntax tree (also known as an “abstract syntax tree”) in other examples, however, a concrete syntax tree as part of the abstract syntax tree, a concrete syntax tree in place of the abstract syntax tree, or other arrangement can be used.

Since, as mentioned above, the compiler 20 can support multiple languages of source code, parsing converts the source code, regardless of the language, into a non-language specific representation, e.g., a syntax tree. Thus, further processing (blocks 114, 116, 118, 120) by the compiler 20 can work from a common input structure regardless of the language of the source code.

As noted above, the syntax tree includes a plurality of operators that are relationally connected. A syntax tree can include multiple different types of operators. For example, different operators can correspond to different functions implemented by the regexes in the source code.

At block 114, the syntax tree is converted into an automaton. An automaton comprises a software model of a FSM which may, for example, comprise a plurality of states. In order to convert the syntax tree into an automaton, the operators and relationships between the operators in the syntax tree are converted into states with transitions between the states. Moreover, in one embodiment, conversion of the automaton is accomplished based on the hardware of the FSM lattice 30.

In an example, input symbols for the automaton include the symbols of the alphabet, the numerals 0-9, and other printable characters. In an example, the input symbols are represented by the byte values 0 through 255 inclusive. In an example, an automaton can be represented as a directed graph where the nodes of the graph correspond to the set of states. In an example, a transition from state p to state q on an input symbol α, i.e. δ(p, α), is shown by a directed connection from node p to node q. In an example, a reversal of an automaton produces a new automaton where each transition p→q on some symbol α is reversed q→p on the same symbol. In a reversal, start states become final states and the final states become start states. In an example, the language recognized (e.g., matched) by an automaton is the set of all possible character strings which when input sequentially into the automaton will reach a final state. Each string in the language recognized by the automaton traces a path from the start state to one or more final states.

At block 116, after the automaton is constructed, the automaton is optimized to reduce its complexity and size, among other things. The automaton can be optimized by combining redundant states.

At block 118, the optimized automaton is converted into a netlist. Converting the automaton into a netlist maps each state of the automaton to a hardware element (e.g., STEs 34, 36, other elements) on the FSM lattice 30, and determines the connections between the hardware elements.

At block 120, the netlist is placed to select a specific hardware element of the target device (e.g., STEs 34, 36, special purpose elements 58) corresponding to each node of the netlist. In an example, placing selects each specific hardware element based on general input and output constraints for of the FSM lattice 30.

At block 122, the placed netlist is routed to determine the settings for the configurable switching elements (e.g., inter-block switching elements 40, intra-block switching elements 42, and intra-row switching elements 44) in order to couple the selected hardware elements together to achieve the connections describe by the netlist. In an example, the settings for the configurable switching elements are determined by determining specific conductors of the FSM lattice 30 that will be used to connect the selected hardware elements, and the settings for the configurable switching elements. Routing can take into account more specific limitations of the connections between the hardware elements than can be accounted for via the placement at block 120. Accordingly, routing may adjust the location of some of the hardware elements as determined by the global placement in order to make appropriate connections given the actual limitations of the conductors on the FSM lattice 30.

Once the netlist is placed and routed, the placed and routed netlist can be converted into a plurality of bits for configuring a FSM lattice 30. The plurality of bits are referred to herein as an image (e.g., binary image).

At block 124, an image is published by the compiler 20. The image comprises a plurality of bits for configuring specific hardware elements of the FSM lattice 30. The bits can be loaded onto the FSM lattice 30 to configure the state of STEs 34, 36, the special purpose elements 58, and the configurable switching elements such that the programmed FSM lattice 30 implements a FSM having the functionality described by the source code. Placement (block 120) and routing (block 122) can map specific hardware elements at specific locations in the FSM lattice 30 to specific states in the automaton. Accordingly, the bits in the image can configure the specific hardware elements to implement the desired function(s). In an example, the image can be published by saving the machine code to a computer readable medium. In another example, the image can be published by displaying the image on a display device. In still another example, the image can be published by sending the image to another device, such as a configuring device for loading the image onto the FSM lattice 30. In yet another example, the image can be published by loading the image onto a FSM lattice (e.g., the FSM lattice 30).

In an example, an image can be loaded onto the FSM lattice 30 by either directly loading the bit values from the image to the STEs 34, 36 and other hardware elements or by loading the image into one or more registers and then writing the bit values from the registers to the STEs 34, 36 and other hardware elements. In an example, the hardware elements (e.g., STEs 34, 36, special purpose elements 58, configurable switching elements 40, 42, 44) of the FSM lattice 30 are memory mapped such that a configuring device and/or computer can load the image onto the FSM lattice 30 by writing the image to one or more memory addresses.

Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, the code may be tangibly stored on one or more volatile or non-volatile computer-readable media during execution or at other times. These computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

Referring now to FIG. 9, an embodiment of the state machine engine 14 (e.g., a single device on a single chip) is illustrated. As previously described, the state machine engine 14 is configured to receive data from a source, such as the memory 16 over a data bus. In the illustrated embodiment, data may be sent to the state machine engine 14 through a bus interface, such as a double data rate (DDR) bus interface 130 (e.g., a DDR3 or a DDR4 bus interface). The DDR bus interface 130 may be capable of exchanging (e.g., providing and receiving) data at a rate greater than or equal to 1 GByte/sec. Such a data exchange rate may be greater than a rate that data is analyzed by the state machine engine 14. As will be appreciated, depending on the source of the data to be analyzed, the bus interface 130 may be any suitable bus interface for exchanging data to and from a data source to the state machine engine 14, such as a NAND Flash interface, peripheral component interconnect (PCI) interface, gigabit media independent interface (GMMI), etc. As previously described, the state machine engine 14 includes one or more FSM lattices 30 configured to analyze data. Each FSM lattice 30 may be divided into two half-lattices. In the illustrated embodiment, each half lattice may include 24K STEs (e.g., STEs 34, 36), such that the lattice 30 includes 48K STEs. The lattice 30 may comprise any desirable number of STEs, arranged as previously described with regard to FIGS. 2-5. Further, while only one FSM lattice 30 is illustrated, the state machine engine 14 may include multiple FSM lattices 30, as previously described.

Data to be analyzed may be received at the bus interface 130 and provided to the FSM lattice 30 through a number of buffers and buffer interfaces. In the illustrated embodiment, the data path includes input buffers 132, an instruction buffer 133, process buffers 134, and an inter-rank (IR) bus and process buffer interface 136. The input buffers 132 are configured to receive and temporarily store data to be analyzed. In one embodiment, there are two input buffers 132 (input buffer A and input buffer B). Data may be stored in one of the two data input 132, while data is being emptied from the other input buffer 132, for analysis by the FSM lattice 30. The bus interface 130 may be configured to provide data to be analyzed to the input buffers 132 until the input buffers 132 are full. After the input buffers 132 are full, the bus interface 130 may be configured to be free to be used for other purpose (e.g., to provide other data from a data stream until the input buffers 132 are available to receive additional data to be analyzed). In the illustrated embodiment, the input buffers 132 may be 32 KBytes each. The instruction buffer 133 is configured to receive instructions from the processor 12 via the bus interface 130, such as instructions that correspond to the data to be analyzed and instructions that correspond to configuring the state machine engine 14. The IR bus and process buffer interface 136 may facilitate providing data to the process buffer 134. The IR bus and process buffer interface 136 can be used to ensure that data is processed by the FSM lattice 30 in order. The IR bus and process buffer interface 136 may coordinate the exchange of data, timing data, packing instructions, etc. such that data is received and analyzed correctly. Generally, the IR bus and process buffer interface 136 allows the analyzing of multiple data sets in parallel through a logical rank of FSM lattices 30. For example, multiple physical devices (e.g., state machine engines 14, chips, separate devices) may be arranged in a rank and may provide data to each other via the IR bus and process buffer interface 136. For purposes of this application the term “rank” refers to a set of state machine engines 14 connected to the same chip select. In the illustrated embodiment, the IR bus and process buffer interface 136 may include a 32 bit data bus. In other embodiments, the IR bus and process buffer interface 136 may include any suitable data bus, such as a 128 bit data bus.

In the illustrated embodiment, the state machine engine 14 also includes a de-compressor 138 and a compressor 140 to aid in providing state vector data through the state machine engine 14. The compressor 140 and de-compressor 138 work in conjunction such that the state vector data can be compressed to minimize the data providing times. By compressing the state vector data, the bus utilization time may be minimized. The compressor 140 and de-compressor 138 can also be configured to handle state vector data of varying burst lengths. By padding compressed state vector data and including an indicator as to when each compressed region ends, the compressor 140 may improve the overall processing speed through the state machine engine 14. The compressor 140 may be used to compress results data after analysis by the FSM lattice 30. The compressor 140 and de-compressor 138 may also be used to compress and decompress configuration data. In one embodiment, the compressor 140 and de-compressor 138 may be disabled (e.g., turned off) such that data flowing to and/or from the compressor 140 and de-compressor 138 is not modified.

As previously described, an output of the FSM lattice 30 can comprise a state vector. The state vector comprises the state (e.g., activated or not activated) of the STEs 34, 36 of the FSM lattice 30 and the dynamic (e.g., current) count of the counter 58. The state machine engine 14 includes a state vector system 141 having a state vector cache memory 142, a state vector memory buffer 144, a state vector intermediate input buffer 146, and a state vector intermediate output buffer 148. The state vector system 141 may be used to store multiple state vectors of the FSM lattice 30 and to provide a state vector to the FSM lattice 30 to restore the FSM lattice 30 to a state corresponding to the provided state vector. For example, each state vector may be temporarily stored in the state vector cache memory 142. For example, the state of each STE 34, 36 may be stored, such that the state may be restored and used in further analysis at a later time, while freeing the STEs 34, 36 for further analysis of a new data set (e.g., search terms). Like a typical cache, the state vector cache memory 142 allows storage of state vectors for quick retrieval and use, here by the FSM lattice 30, for instance. In the illustrated embodiment, the state vector cache memory 142 may store up to 512 state vectors.

As will be appreciated, the state vector data may be exchanged between different state machine engines 14 (e.g., chips) in a rank. The state vector data may be exchanged between the different state machine engines 14 for various purposes such as: to synchronize the state of the STEs 34, 36 of the FSM lattices 30 of the state machine engines 14, to perform the same functions across multiple state machine engines 14, to reproduce results across multiple state machine engines 14, to cascade results across multiple state machine engines 14, to store a history of states of the STEs 34, 36 used to analyze data that is cascaded through multiple state machine engines 14, and so forth. Furthermore, it should be noted that within a state machine engine 14, the state vector data may be used to quickly configure the STEs 34, 36 of the FSM lattice 30. For example, the state vector data may be used to restore the state of the STEs 34, 36 to an initialized state (e.g., to prepare for a new input data set), or to restore the state of the STEs 34, 36 to prior state (e.g., to continue searching of an interrupted or “split” input data set). In certain embodiments, the state vector data may be provided to the bus interface 130 so that the state vector data may be provided to the processor 12 (e.g., for analysis of the state vector data, reconfiguring the state vector data to apply modifications, reconfiguring the state vector data to improve efficiency of the STEs 34, 36, and so forth).

For example, in certain embodiments, the state machine engine 14 may provide cached state vector data (e.g., data stored by the state vector system 141) from the FSM lattice 30 to an external device. The external device may receive the state vector data, modify the state vector data, and provide the modified state vector data to the state machine engine 14 for configuring the FSM lattice 30. Accordingly, the external device may modify the state vector data so that the state machine engine 14 may skip states (e.g., jump around) as desired.

The state vector cache memory 142 may receive state vector data from any suitable device. For example, the state vector cache memory 142 may receive a state vector from the FSM lattice 30, another FSM lattice 30 (e.g., via the IR bus and process buffer interface 136), the de-compressor 138, and so forth. In the illustrated embodiment, the state vector cache memory 142 may receive state vectors from other devices via the state vector memory buffer 144. Furthermore, the state vector cache memory 142 may provide state vector data to any suitable device. For example, the state vector cache memory 142 may provide state vector data to the state vector memory buffer 144, the state vector intermediate input buffer 146, and the state vector intermediate output buffer 148.

Additional buffers, such as the state vector memory buffer 144, state vector intermediate input buffer 146, and state vector intermediate output buffer 148, may be utilized in conjunction with the state vector cache memory 142 to accommodate rapid retrieval and storage of state vectors, while processing separate data sets with interleaved packets through the state machine engine 14. In the illustrated embodiment, each of the state vector memory buffer 144, the state vector intermediate input buffer 146, and the state vector intermediate output buffer 148 may be configured to temporarily store one state vector. The state vector memory buffer 144 may be used to receive state vector data from any suitable device and to provide state vector data to any suitable device. For example, the state vector memory buffer 144 may be used to receive a state vector from the FSM lattice 30, another FSM lattice 30 (e.g., via the IR bus and process buffer interface 136), the de-compressor 138, and the state vector cache memory 142. As another example, the state vector memory buffer 144 may be used to provide state vector data to the IR bus and process buffer interface 136 (e.g., for other FSM lattices 30), the compressor 140, and the state vector cache memory 142.

Likewise, the state vector intermediate input buffer 146 may be used to receive state vector data from any suitable device and to provide state vector data to any suitable device. For example, the state vector intermediate input buffer 146 may be used to receive a state vector from an FSM lattice 30 (e.g., via the IR bus and process buffer interface 136), the de-compressor 138, and the state vector cache memory 142. As another example, the state vector intermediate input buffer 146 may be used to provide a state vector to the FSM lattice 30. Furthermore, the state vector intermediate output buffer 148 may be used to receive a state vector from any suitable device and to provide a state vector to any suitable device. For example, the state vector intermediate output buffer 148 may be used to receive a state vector from the FSM lattice 30 and the state vector cache memory 142. As another example, the state vector intermediate output buffer 148 may be used to provide a state vector to an FSM lattice 30 (e.g., via the IR bus and process buffer interface 136) and the compressor 140.

Once a result of interest is produced by the FSM lattice 30, an event vector may be stored in a event vector memory 150, whereby, for example, the event vector indicates at least one search result (e.g., detection of a pattern of interest). The event vector can then be sent to an event buffer 152 for transmission over the bus interface 130 to the processor 12, for example. As previously described, the results may be compressed. The event vector memory 150 may include two memory elements, memory element A and memory element B, each of which contains the results obtained by processing the input data in the corresponding input buffers 132 (e.g., input buffer A and input buffer B). In one embodiment, each of the memory elements may be DRAM memory elements or any other suitable storage devices. In some embodiments, the memory elements may operate as initial buffers to buffer the event vectors received from the FSM lattice 30, along results bus 151. For example, memory element A may receive event vectors, generated by processing the input data from input buffer A, along results bus 151 from the FSM lattice 30. Similarly, memory element B may receive event vectors, generated by processing the input data from input buffer B, along results bus 151 from the FSM lattice 30.

In one embodiment, the event vectors provided to the event vector memory 150 may indicate that a final result has been found by the FSM lattice 30. For example, the event vectors may indicate that an entire pattern has been detected. Alternatively, the event vectors provided to the event vector memory 150 may indicate, for example, that a particular state of the FSM lattice 30 has been reached. For example, the event vectors provided to the event vector memory 150 may indicate that one state (i.e., one portion of a pattern search) has been reached, so that a next state may be initiated. In this way, the event vector memory 150 may store a variety of types of results.

In some embodiments, IR bus and process buffer interface 136 may provide data to multiple FSM lattices 30 for analysis. This data may be time multiplexed. For example, if there are eight FSM lattices 30, data for each of the eight FSM lattices 30 may be provided to all of eight IR bus and process buffer interfaces 136 that correspond to the eight FSM lattices 30. Each of the eight IR bus and process buffer interfaces 136 may receive an entire data set to be analyzed. Each of the eight IR bus and process buffer interfaces 136 may then select portions of the entire data set relevant to the FSM lattice 30 associated with the respective IR bus and process buffer interface 136. This relevant data for each of the eight FSM lattices 30 may then be provided from the respective IR bus and process buffer interfaces 136 to the respective FSM lattice 30 associated therewith.

The event vector memory 150 may operate to correlate each received result with a data input that generated the result. To accomplish this, a respective result indicator may be stored corresponding to, and in some embodiments, in conjunction with, each event vector received from the results bus 151. In one embodiment, the result indicators may be a single bit flag. In another embodiment, the result indicators may be a multiple bit flag. If the result indicators may include a multiple bit flag, the bit positions of the flag may indicate, for example, a count of the position of the input data stream that corresponds to the event vector, the lattice that the event vectors correspond to, a position in set of event vectors, or other identifying information. These results indicators may include one or more bits that identify each particular event vector and allow for proper grouping and transmission of event vectors, for example, to compressor 140. Moreover, the ability to identify particular event vectors by their respective results indicators may allow for selective output of desired event vectors from the event vector memory 150. For example, only particular event vectors generated by the FSM lattice 30 may be selectively latched as an output. These result indicators may allow for proper grouping and provision of results, for example, to compressor 140. Moreover, the ability to identify particular event vectors by their respective result indicators allow for selective output of desired event vectors from the event vector memory 150. Thus, only particular event vectors provided by the FSM lattice 30 may be selectively provided to compressor 140.

Additional registers and buffers may be provided in the state machine engine 14, as well. In one embodiment, for example, a buffer may store information related to more than one process whereas a register may store information related to a single process. For instance, the state machine engine 14 may include control and status registers 154. In addition, a program buffer system (e.g., restore buffers 156) may be provided for initializing the FSM lattice 30. For example, initial (e.g., starting) state vector data may be provided from the program buffer system to the FSM lattice 30 (e.g., via the de-compressor 138). The de-compressor 138 may be used to decompress configuration data (e.g., state vector data, routing switch data, STE 34, 36 states, Boolean function data, counter data, match MUX data) provided to program the FSM lattice 30.

Similarly, a repair map buffer system (e.g., save buffers 158) may also be provided for storage of data (e.g., save maps) for setup and usage. The data stored by the repair map buffer system may include data that corresponds to repaired hardware elements, such as data identifying which STEs 34, 36 were repaired. The repair map buffer system may receive data via any suitable manner. For example, data may be provided from a “fuse map” memory, which provides the mapping of repairs done on a device during final manufacturing testing, to the save buffers 158. As another example, the repair map buffer system may include data used to modify (e.g., customize) a standard programming file so that the standard programming file may operate in a FSM lattice 30 with a repaired architecture (e.g., bad STEs 34, 36 in a FSM lattice 30 may be bypassed so they are not used). The compressor 140 may be used to compress data provided to the save buffers 158 from the fuse map memory. As illustrated, the bus interface 130 may be used to provide data to the restore buffers 156 and to provide data from the save buffers 158. As will be appreciated, the data provided to the restore buffers 156 and/or provided from the save buffers 158 may be compressed. In some embodiments, data is provided to the bus interface 130 and/or received from the bus interface 130 via a device external to the state machine engine 14 (e.g., the processor 12, the memory 16, the compiler 20, and so forth). The device external to the state machine engine 14 may be configured to receive data provided from the save buffers 158, to store the data, to analyze the data, to modify the data, and/or to provide new or modified data to the restore buffers 156.

The state machine engine 14 includes a lattice programming and instruction control system 159 used to configure (e.g., program) the FSM lattice 30 as well as provide inserted instructions, as will be described in greater detail below. As illustrated, the lattice programming and instruction control system 159 may receive data (e.g., configuration instructions) from the instruction buffer 133. Furthermore, the lattice programming and instruction control system 159 may receive data (e.g., configuration data) from the restore buffers 156. The lattice programming and instruction control system 159 may use the configuration instructions and the configuration data to configure the FSM lattice 30 (e.g., to configure routing switches, STEs 34, 36, Boolean cells, counters, match MUX) and may use the inserted instructions to correct errors during the operation of the state machine engine 14. The lattice programming and instruction control system 159 may also use the de-compressor 138 to de-compress data and the compressor 140 to compress data (e.g., for data exchanged with the restore buffers 156 and the save buffers 158).

FIG. 10 illustrates a second embodiment of a processor-based system, generally designated by reference numeral 160. The state machine engine 14 is not a conventional memory device, yet it may use a memory interface (such as DDR bus interface 130) to interface to the system 160. The state machine engine 14 inherently operates on large blocks of data—the data to program or configure the FSM lattice 30, the data to fill the Instruction buffer 133, the input data to process, and the output data, and the like. Direct Memory Access (DMA) is a way to move large blocks of data between two different memory blocks or between an I/O device and a memory block, without the main system CPU (e.g., processor 12) performing every read or write. Using DMA allows the CPU (e.g., processor 12) to perform other tasks, while the state machine engine 14 data is being transferred. Effectively using DMA requires the hardware of the state machine engine 14 to be able to be accessed by a DMA controller 162. It also requires the system CPU (e.g., processor 12) to either know or be able to find out how much data to transfer, what “starting addresses” to set up, and whether to use the “auto-increment” or the “same address” mode. For the state machine engine 14, this may include hardware to be designed into state machine engine 14 and/or a software driver (e.g., in processor 12 or DMA controller 162, for example, in control logic 164) to be able to control the DMA processing. To implement DMA transfers, the system 160 includes a processor 12, a state machine engine 14, a memory 16, external storage 18, a compiler 20, an input device 22, an output device 24, and a network interface device 26 similar to those discussed above with respect to FIG. 1 as well as the DMA controller 162.

The DMA controller 162 may be used to transfer data in the system separate from the processor 12. For example, processor 12 may utilize a list of commands, or instructions, to operate, which are often grouped together as a program and stored in memory 16. Accessing of the memory 16 may require a certain amount of time, during which time the processor 12 idly waits. The DMA controller 162 also may be utilized to transfer data between a location in memory 16 and the state machine engine 14, the external storage 18, the input device 22, the output device 24, and/or the network interface device 26. Similarly, the DMA controller 162 also may be utilized to transfer data between the state machine engine 14, the external storage 18, the input device 22, the output device 24, and/or the network interface device 26 and a location in memory 16. In some embodiments, the control logic 164 may be utilized to facilitate these data transfers. The DMA controller 162 also may be used to transfer data between two locations in memory 16, or directly between the state machine engine 14, the external storage 18, the input device 22, the output device 24, and/or the network interface device 26. Similarly, the control logic 164 may be utilized to facilitate these data transfers. In this manner, the DMA controller 162 may generally operate to transfer data between a data source and a data sink.

Furthermore, the DMA controller 162 can reduce the time the processor 12 remains remain idle. For example, the processor 12 may hand off the fetching of a list of instructions grouped together as a program to the DMA controller 162. The processor 12 may then be free to execute previously fetched instructions or perform other computing tasks while the DMA controller 162 fetches the requested program for the processor 12. In some embodiments the DMA controller 162 may also facilitate a reduction in an amount of down time of the processor 12 related to the operation of the state machine engine 14.

For example, the state machine engine 14 may operate under the indirect control of the processor 12, whereby the processor 12 transmits programming/configuration information, data searching/analyzing instructions, requests, indications of data to be searched, and the like to the DMA controller 162. The DMA controller 162 may then undertake control of the state machine engine 14 so that the processor 12 may be utilized for other tasks during the operation of the state machine engine. When one or more results are generated by the state machine engine 14, these results may be transmitted, for example to the DMA controller 162. The DMA controller 162 may, for example, store the results in memory 16 or the results may be transmitted directly to memory 16 for access by the DMA controller 162. Subsequently, the DMA controller 162 may transmit an indication to the processor 12 that results of an analysis or search have been received by the DMA controller 162. The processor 12 may request these results from the DMA controller 162 subsequent to receiving the above-noted indication from the DMA controller 162. In this manner, the processor 12 can actively determine when to receive the state machine engine 14 results and may operate on separate tasks while the state machine engine 14 search or analysis is being undertaken.

DMA, as well as normal CPU reads/writes, may be utilized to move data between the system 160 (e.g., processor 12) and the state machine engine 14. Because the DDR memory bus (coupled to DDR bus interface 130) is capable of transferring data much faster than the state machine engine 14 can consume or provide the data, there are several buffers built into the state machine engine 14 architecture and/or the DMA controller 162. Each buffer, of necessity, has unique DMA requirements, which are presented, below.

There are two classes of buffers: 1) Buffers designed to provide inputs to the FSM lattice 30, e.g., for processing, and 2) buffers designed to provide output from the FSM lattice 30, e.g., to the host system 160. The input buffers may include the instruction buffer 133, input buffers A and B 132, and restore buffers A and B 156. Similarly, output buffers may include save buffers A and B 158 and event buffers A and B 152. In conjunction with the operation of system 160, each of the respective input and output buffers can be filled or emptied, using DMA operations from the system 160 (e.g., via DMA controller 162). However, alternative operation separate from that used in conjunction with system 10 may be utilized to allow for DMA operations to be implemented in conjunction with the state machine engine 14.

Thus, to properly execute the transfers to and from the state machine engine 14, the DMA controller 162 must be able to properly access the state machine engine 14. For example, information related to how much data may be transferred to the state machine engine 14, what starting addresses should be provided to the state machine engine 14, which (if any) operating modes are being utilized by the state machine engine 14, and the like. This information may, for example, be determined or retrieved by the processor 12 and utilized to appropriately structure any DMA transfers from the DMA controller 162 of data to the state machine engine 14 appropriately. Thus, various factors, for example, variable data lengths being transmitted to the state machine engine 14, variable instruction lengths being transmitted to the state machine engine 14, and/or variable output data lengths being transmitted from the state machine engine 14 each may cause potential difficulties in structuring DMA transfers to and from the state machine engine 14.

Returning again to FIG. 9, the instruction buffer 133 may receive and store instructions received from, for example, the processor 12 as part of a DMA transfer to the state machine engine 14. In some embodiments, these instructions may include instructions that correspond to the data to be analyzed and instructions that correspond to configuring (e.g., initializing or setting up) the state machine engine 14. However, these instructions may be of variable lengths. For example, the processor 12 may transmit more instructions as part of one transmission than may be receivable at one time by the state machine engine 14. Accordingly, the instruction buffer 133 may be utilized to queue the state machine engine 14 instruction for transmission to, for example, the programming and instruction control system 159 so that the state machine engine 14 may properly handle the instructions. In this manner, the instruction buffer 133 may be a handling buffer.

To operate in conjunction with either system or DMA writes, the instruction buffer 133 may be designed as a circular buffer that is filled by the system 160 via the DMA or system writes. The instruction buffer 133 is also emptied by the state machine engine 14, as it processes the instructions controlling the operation of the state machine engine 14. The DMA controller 162 may utilize an address to which it can write, whereby the address does not fluctuate. Therefore, the state machine engine 14 accepts writes (either DMA or system writes) to a fixed address on the DDR bus, but places the data into the circular buffer of the instruction buffer 133 at the proper location in the buffer 133. The state machine engine 14 may employ pointers to determine exactly which byte, in the instruction buffer 133, to read when emptying and to write when filling. Through this mechanism, the DMA controller 162 may perform in a manner that approximates a normal memory to fixed I/O address DMA operation, while the state machine engine 14 automatically handles the translation of the transmitted instructions to (and from) the appropriate point in the instruction buffer 133.

The input buffers A and B 132 may also receive and store data may receive and store instructions received from, for example, the processor 12 as part of a DMA transfer to the state machine engine 14. The data stored in the input buffers A and B 132 may, in some embodiments, correspond to data to be searched by the state machine engine 14. However, as the data indicated by the processor 12 to be transmitted to the state machine engine 14 may be variable in length, the input buffers A and B 132 may operate to reorganize the data so that is may be properly received for operation by the state machine engine 14.

In some embodiments, the data may be stored in the input buffers A and B 132 as one block of memory or, in some embodiments, as two blocks of memory (e.g., each block corresponding to a logical half-lattice of an FSM lattice 30). These input buffers A and B 132 deliver the data, which is to be processed, to the FSM lattice 30. DMA operations to the FSM lattice 30 is also handled in an atypical manner, due to the hardware configuration of the state machine elements (e.g., having multiple FSM lattices 30 per rank connected via an intra-rank bus). A state machine engine 14 utilizing only one FSM lattice 30 may utilize one continuous buffer (e.g., one or both of input buffers A and B 132) and, thus, a normal DMA operation may be implemented to transfer data from the host 160 to the state machine engine 14. However, when the state machine engine 14 makes use of multiple FSM lattices 30 in the rank, traditional DMA operations will not be sufficient to transfer data from the host 160 to the state machine engine 14.

To overcome this difficulty, each of the input buffers A and B 132 may be divided into a number of pieces, whereby each piece matches the number of FSM lattices 30. Thus, for four FSM lattices 30, each of the input buffers A and B 132 may be divided into four pieces (e.g., regions), whereby each piece of the input buffer A 132 corresponds to a respective half-lattice 0 of a respective FSM lattice 30 and each piece of the input buffer B 132 corresponds to a respective half-lattice 1 of a respective FSM lattice 30. However, in some embodiments, each piece of the input buffers A and B 132 need not be continuous. For example, each buffer piece may be interleaved with other input buffer pieces so that the data stored therein may be read out in an interleaved manner.

Indeed, in some embodiments, the data stored in each of input buffer A 132 and input buffer B 132 may be interleaved data. For example, input buffer A 132 and input buffer B 132 may transmit data to be searched by more than one FSM lattice 30. Accordingly, the data input from the input buffer A 132 and input buffer B 132 may be time division multiplexed such that each FSM lattice 30 provided data by the input buffer A 132 and input buffer B 132 receives data proportional to the number of FSM lattices 30. For example, if there are two FSM lattices 30 receiving data, each FSM lattice 30 may receive data during one half of a time period for data transmission. Likewise, if there are four FSM lattices 30 receiving data, each FSM lattice 30 may receive data during one quarter of a time period for data transmission. In this manner, data transmitted from the input buffer A 132 and input buffer B 132 is time division multiplexed and the IR bus and process buffer interface 136 may select the appropriate multiplexed data for transmission to a given process buffer 134.

To facilitate the multiplexing of data described above, the data may be stored in each of the input buffer A 132 and input buffer B 132 in an interleaved manner. For example, if there are two FSM lattices 30 receiving data, the data stored in the each of the input buffer A 132 and input buffer B 132 may be interleaved such that the first data for a first FSM lattice 30 is stored in a first memory position, first data for the second FSM lattice 30 is stored in a second memory position directly adjacent to the first memory position, second data for the first FSM lattice 30 is stored in a third memory position directly adjacent to the second memory position, and so forth. Similarly, if there are four FSM lattices 30 receiving data, the data stored in the each of the input buffer A 132 and input buffer B 132 may be interleaved such that the first data for a first FSM lattice 30 is stored in a first memory position, first data for the second FSM lattice 30 is stored in a second memory position directly adjacent to the first memory position, first data for the third FSM lattice 30 is stored in a third memory position directly adjacent to the second memory position, first data for the fourth FSM lattice 30 is stored in a fourth memory position directly adjacent to the third memory position, second data for the first FSM lattice 30 is stored in a fifth memory position directly adjacent to the fourth memory position, second data for the second FSM lattice 30 is stored in a sixth memory position directly adjacent to the fifth memory position, and so forth.

As with the instruction buffer 133 discussed above, the state machine engine 14 may accept writes (either DMA or system) to a fixed address on the DDR bus, however, the state machine engine 14 may transmit the data into input buffers A and B 132 at the proper locations. Additionally, hardware pointers may be implemented to determine exactly where to write when filling the input buffers A and B 132 with data. Through this mechanism, the DMA controller 162 performs normal memory to fixed I/O address DMA operations, while the state machine engine 14 automatically handles the translation to the appropriate point in the input buffers A and B 132. Additionally, in some embodiments, different fixed address may be used by the DMA controller 162, depending upon the number of logical cores being used by the state machine engine 14 (e.g., a different address corresponding to each FSM lattice 30).

Turning to restore buffers A and B 156, restore buffers A and B 156 may be accessed via the DMA controller 162 without any alteration by the state machine engine 14. This is in contrast to the other buffers designed to provide inputs to the FSM lattice 30, e.g., the input buffers including the instruction buffer 133 and the input buffers A and B 132, in which the state machine engine 14 handles translation of the DMA access into particular portions of the accessed buffer. Such translation may not need to be completed to allow the DMA controller 162 to transfer instructions and/or data to the restore buffers A and B 156.

As previously noted, the state machine engine 14 may include buffers designed to provide output from the FSM lattice 30, e.g., to the host system 160. These output buffers may include the save buffers A and B 158 and event buffers A and B 152. With respect to save buffers A and B 158, the save buffers A and B 158 may be loaded by the state machine engine during execution of one or more instructions of the instruction buffer 133 (e.g., as the state machine engine 14 is executing one or more instructions of the instruction buffer 133). The loading of the save buffers A and B 158 may include the loading of various types of data, including repair map data (e.g., data that corresponds to repaired hardware elements, such as data identifying which STEs 34, 36 were repaired) and state vector data (e.g., the states of the elements of the FSM 30 at a given time). The data stored in the save buffers A and B 158 may be straight (uncompressed) data or compressed data, as controlled by instructions from the state machine engine. Accordingly, as the save buffers A and B 158 may include data of variable lengths, there must be a mechanism to alert the host system 160 of the DMA length to set up. In some embodiments, a hardware register (e.g., stored internal to or separate from the save buffers A and B 158) may be updated with the count of the number of bytes of data present in one or more of the save buffers A and B 158. This count may be read by the host system 160 or transmitted to the host system 160 so that the host system may set up the DMA controller 162 accordingly (e.g., initialize the DMA controller to receive or retrieve the correct amount of data from one or more of the save buffers A and B 158).

Additionally, event buffers A and B 152 may operate in a manner similar to the save buffers A and B 158 described above. However, in place of the repair map data and/or the state vector data stored in the save buffers A and B 158, the event buffers save buffers A and B 152 store the results of the FSM 30 processing. Accordingly the data stored in the event buffers A and B 152 (in either compressed or uncompressed form) may include data with greater variations in length than that stored in the save buffers A and B 158. To allow for accurate DMA transfers of the data stored in the event buffers A and B 152, a hardware register (e.g., stored internal to or separate from the event buffers A and B 152) may be updated with the count of the number of bytes of data present in one or more of the event buffers A and B 152. This count may be read by the host system 160 or transmitted to the host system 160 so that the host system may set up the DMA controller 162 accordingly (e.g., initialize the DMA controller to receive or retrieve the correct amount of data from one or more of the event buffers A and B 152). It may be appreciated that the hardware register storing the count for the event buffers A and B 152 and the hardware register storing the count for the save buffers A and B 158 may be a single register that is segmented to provide separate counts corresponding to each of the event buffers A and B 152 and the save buffers A and B 158. Alternatively, separate hardware registers may be utilized in conjunction with each of the event buffers A and B 152 and the save buffers A and B 158.

The output buffers (e.g., the event buffers A and B 152 and the save buffers A and B 158) may present specific complications to the DMA process being implemented by the host system 160. For example, problems may be encountered when there are multiple state machine engines 14 that are each configured to operate as a single DDR rank. In addition to the data length of the event buffers A and B 152 and the save buffers A and B 158 of a state machine engine 14 being variable, each state machine engine 14 can and will most often have different lengths it its respective output buffers relative to the other state machine engines 14 for the same DMA operation by DMA controller 162.

A process and system may be implemented to account for this situation. Each state machine engine 14 already provides the count of the number of bytes in the respective buffers (e.g., the event buffers A and B 152 and the save buffers A and B 158). The host system 160 may read those byte counts, determine the greatest number of bytes contained in any of the state machine engines 14 buffers (e.g., the event buffers A and B 152 and the save buffers A and B 158), round up to the nearest 8-byte burst boundary, then set the DMA operation to read that final number of bytes from the state machine engines 14 buffers. In some embodiments, when a respective the buffer is empty, the respective state machine engine 14 keeps outputting all zeroes (e.g., 0x00) for any subsequent DDR DMA read cycles. Since the host system 160 already has the number of real or valid bytes that were in each state machine engines 14 buffers, the host system 160 can separate the valid data from the end padding zeroes.

While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims. 

What is claimed is:
 1. A device, comprising: an instruction buffer, wherein the instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a finite state machine lattice, wherein the finite state machine lattice comprises configurable elements configured to analyze the at least a portion of the data stream and to selectively output a result of the analysis, wherein the instruction buffer is configured to receive the instructions from a DMA controller external to the device comprising the instruction buffer as part of a direct memory access (DMA) transfer to the device comprising the instruction buffer, wherein the device is configured to accept writes to a fixed address on a DDR bus and place the instructions into a translated variable location in the instruction buffer.
 2. The device of claim 1, wherein the instruction buffer is configured to store instructions related to setting up the finite state machine lattice.
 3. The device of claim 1, wherein the instruction buffer is configured to store the instructions as variable length values.
 4. The device of claim 1, wherein the instruction buffer is configured to transmit the instructions to portions of the device corresponding to the respective instructions.
 5. The device of claim 4, comprising a lattice control system, wherein the instruction buffer is configured to transmit the instructions to the lattice control system to program the finite state machine lattice.
 6. The device of claim 4, wherein the instruction buffer is configured to receive the instructions from a DDR3 bus interface or DDR4 bus interface.
 7. The device of claim 1, comprising a state machine engine as the device.
 8. The device of claim 7, wherein the state machine engine is configured to utilize a pointer to determine which byte in the instruction buffer to read from when emptying the instruction buffer and determine which byte in the instruction buffer to write to when filling the instruction buffer.
 9. A device, comprising: an input buffer, wherein the input buffer is configured to store at least a portion of a data stream to be analyzed by a finite state machine lattice, wherein the finite state machine lattice comprises configurable elements configured to analyze the at least a portion of the data stream and to selectively output a result of the analysis, wherein the input buffer is configured to receive the at least a portion of the data stream from a DMA controller external to the device comprising the input buffer as part of a direct memory access (DMA) transfer to the device comprising the input buffer, wherein the device is configured to accept writes to a fixed address on a DDR bus and place the at least a portion of the data stream into a translated variable location in the input buffer.
 10. The device of claim 9, wherein the input buffer comprises a first portion and a second portion, wherein the first portion corresponds to a first half-lattice of the finite state machine lattice comprising a first set of configurable elements of the configurable elements, wherein the second portion corresponds to a second half-lattice of the finite state machine lattice comprising a second set of configurable elements of the configurable elements.
 11. The device of claim 10, wherein the input buffer is configured to read out the portion of the data stream in a different order than an order in which the portion of the data stream was received.
 12. The device of claim 11, wherein the input buffer is configured to read out the portion of the data stream in an interleaved manner as interleaved data.
 13. The device of claim 12, comprising a bus interface, wherein the input buffer is configured to transmit the interleaved data to the finite state machine lattice via the bus interface.
 14. The device of claim 9, wherein the input buffer is configured to receive the portion of the data stream from a DDR3 bus interface or DDR4 bus interface.
 15. The device of claim 9, comprising a state machine engine as the device.
 16. The device of claim 15, wherein the state machine engine is configured to accept writes to a second fixed address on the DDR bus and place at least a second portion of the data stream into a second proper location in the input buffer, wherein the first proper location corresponds to the finite state machine lattice, wherein the second proper location corresponds to a second finite state machine lattice, wherein the second finite state machine lattice corresponds to a second set of configurable elements configured to analyze the at least the second portion of the data stream and to selectively output the result of the analysis.
 17. A device, comprising: an output buffer, wherein the output buffer is configured to store data related to at least a portion of a data stream analyzed by a finite state machine lattice, wherein the finite state machine lattice comprises configurable elements configured to analyze the at least a portion of the data stream and to selectively output a result of the analysis, wherein the output buffer is configured to transmit the data as part of a direct memory access (DMA) transfer from the device to a DMA controller external to the device comprising the output buffer; and a register configured to store a count related to a number of bits of the data to facilitate the DMA transfer of the data through configuration of the DMA controller to receive DMA transfers having data of variable lengths based on the count.
 18. The device of claim 17, wherein the output buffer comprises a restore buffer configured to store state vector data related to a state of the finite state machine lattice subsequent to the analysis of the at least a portion of the data stream.
 19. The device of claim 18, wherein the restore buffer is configured to transmit the state vector data as part of a direct memory access (DMA) transfer.
 20. The device of claim 19, comprising a register configured to store a count related to a number of bits of state vector data to facilitate the DMA transfer.
 21. The device of claim 17, wherein the output buffer comprises an event buffer configured to store an event vector indicative of at least one search result as the result of the analysis.
 22. The device of claim 21, wherein the event buffer is configured to append dummy bits to the event vector to generate an adjusted event vector.
 23. The device of claim 21, wherein the event buffer is configured to transmit the event vector as part of a direct memory access (DMA) transfer.
 24. The device of claim 17, comprising a state machine engine as the device.
 25. A device comprising: a buffer configured to be accessed by a direct memory access (DMA) controller external to the device comprising the buffer during a DMA transfer of variable length inputs between the DMA controller and the device comprising the buffer, wherein the device further comprises a finite state machine lattice, wherein the finite state machine lattice comprises configurable elements configured to analyze at least a portion of a data stream and to selectively output a result of the analysis, wherein the buffer is configured to store at least one of an instruction or a data as a portion of the variable length inputs at a translated variable location in the buffer.
 26. The device of claim 25, wherein the buffer includes an instruction buffer configured to store the instruction as related to the at least a portion of the data stream to be analyzed by the finite state machine lattice.
 27. The device of claim 25, wherein the buffer includes an input buffer configured to store the data as a portion of the data stream.
 28. The device of claim 25, comprising a state machine engine as the device.
 29. A system, comprising: a processor; a direct memory access (DMA) controller coupled to the processor, wherein the processor is configured to determine variable data length portions of a data stream for transfer from the DMA controller and structure DMA transfers having variable data lengths from the DMA controller based on the determined variable data length portions of the data stream; and a state machine engine comprising a buffer and a finite state machine lattice, wherein the state machine engine is external to the DMA controller, wherein the buffer is configured to be accessed by the DMA controller during a DMA transfer between the DMA controller and the state machine engine comprising the buffer and a finite state machine lattice, wherein the finite state machine lattice comprises configurable elements configured to analyze at least a portion of the data stream and to selectively output a result of the analysis, wherein the buffer is configured to store at least one of an instruction or a data related to the data stream.
 30. The system of claim 29, comprising the state machine engine, wherein the state machine engine comprises: a second finite state machine lattice, wherein the second finite state machine lattice corresponds to a second set of configurable elements of the state machine engine configured to analyze at least a second portion of the data stream and to selectively output the result of the analysis.
 31. The system of claim 30, wherein the buffer includes an input buffer configured to store the at least a portion of the data stream to be analyzed by the finite state machine lattice and the at least a second portion of the data stream to be analyzed by the second finite state machine lattice, wherein the state machine engine is configured to accept writes to a fixed address on a DDR bus and place the at least a portion of the data stream into a proper location in the input buffer.
 32. The system of claim 31, wherein the state machine engine is configured to accept writes to a second fixed address on the DDR bus and place at least a second portion of the data stream into a second proper location in the input buffer, wherein the first proper location corresponds to the finite state machine lattice of the state machine engine, wherein the second proper location corresponds to the second finite state machine lattice of the state machine engine.
 33. The system of claim 30, wherein the buffer includes an input buffer configured to be divided into pieces that correspond to the first finite state machine lattice and the second finite state machine lattice, respectively.
 34. The system of claim 33, wherein the input buffer is configured to store the at least a portion of the data stream in a first piece of the input buffer and to store the at least a second portion of the data stream in a second piece of the input buffer.
 35. The system of claim 29, comprising a second state machine engine comprising a second buffer, wherein the state machine engine and the second state machine engine are configured to provide a respective count of the number of bytes in their respective buffer to the DMA controller.
 36. The system of claim 35, wherein the state machine engine and the second state machine engine are configured to output all zeroes as end padding zero data for any subsequent DDR DMA read cycles when the buffer of the first state machine engine or the buffer of the second state machine engine is empty.
 37. The system of claim 36, wherein the DMA controller is configured to recognize and separate the end padding zero data received from the state machine engine or the second state machine engine. 